spi.h

Go to the documentation of this file.

//   Copyright 2016-2023 Jean-Francois Poilpret
//
//   Licensed under the Apache License, Version 2.0 (the "License");
//   you may not use this file except in compliance with the License.
//   You may obtain a copy of the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in writing, software
//   distributed under the License is distributed on an "AS IS" BASIS,
//   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//   See the License for the specific language governing permissions and
//   limitations under the License.
 
 
#ifndef FASTSPI_HH
#define FASTSPI_HH
 
#include "boards/board.h"
#include "gpio.h"
 
namespace spi
{
    void init();
 
    enum class ClockRate : uint8_t
    {
        CLOCK_DIV_4 = 0x00,
        CLOCK_DIV_16 = 0x01,
        CLOCK_DIV_64 = 0x02,
        CLOCK_DIV_128 = 0x03,
        CLOCK_DIV_2 = 0x10,
        CLOCK_DIV_8 = 0x11,
        CLOCK_DIV_32 = 0x12
    };
 
    constexpr ClockRate compute_clockrate(uint32_t frequency)
    {
        if (frequency >= (F_CPU / 2))
            return ClockRate::CLOCK_DIV_2;
        else if (frequency >= (F_CPU / 4))
            return ClockRate::CLOCK_DIV_4;
        else if (frequency >= (F_CPU / 8))
            return ClockRate::CLOCK_DIV_8;
        else if (frequency >= (F_CPU / 16))
            return ClockRate::CLOCK_DIV_16;
        else if (frequency >= (F_CPU / 32))
            return ClockRate::CLOCK_DIV_32;
        else if (frequency >= (F_CPU / 64))
            return ClockRate::CLOCK_DIV_64;
        else
            return ClockRate::CLOCK_DIV_128;
    }
 
#ifdef SPDR
    enum class DataOrder : uint8_t
    {
        MSB_FIRST = 0,
        LSB_FIRST = bits::BV8(DORD)
    };
#else
    enum class DataOrder : uint8_t
    {
        MSB_FIRST = 0
    };
#endif
 
#ifdef SPDR
    enum class Mode : uint8_t
    {
        MODE_0 = 0,
        MODE_1 = bits::BV8(CPHA),
        MODE_2 = bits::BV8(CPOL),
        MODE_3 = bits::BV8(CPHA, CPOL)
    };
#else
    enum class Mode : uint8_t
    {
        MODE_0 = bits::BV8(USIWM0, USICLK, USICS1),
        MODE_1 = bits::BV8(USIWM0, USICLK, USICS1, USICS0)
    };
#endif
 
    enum class ChipSelect : uint8_t
    {
        ACTIVE_LOW = 0,
        ACTIVE_HIGH = 1
    };
 
    class AbstractSPIDevice
    {
    protected:
        AbstractSPIDevice() = default;
        AbstractSPIDevice(const AbstractSPIDevice&) = delete;
        AbstractSPIDevice& operator=(const AbstractSPIDevice&) = delete;
 
#ifdef SPDR
        uint8_t transfer(uint8_t data)
        {
            SPDR_ = data;
            SPSR_.loop_until_bit_set(SPIF);
            return SPDR_;
        }
#else
        uint8_t transfer(uint8_t data)
        {
            USIDR_ = data;
            // Clear counter overflow before transmission
            USISR_ = bits::BV8(USIOIF);
            synchronized
            {
                // Note: the following loop means 7 clock cycles per bit transmitted
                // Hence at 8MHz, that gives a SPI rate > 1MHz, which might be incompatible 
                // with some devices
                // FIXME add a NOP to ensure 8 clock cycles per bit, hence 1MHz SPI clock
                while ((USISR_ & bits::BV8(USIOIF)) == 0) USICR_ |= bits::BV8(USITC);
            }
            return USIDR_;
        }
#endif
 
        void transfer(uint8_t* data, uint16_t size)
        {
            while (size--)
            {
                uint8_t value = *data;
                *data++ = transfer(value);
            }
        }
 
        void transfer(const uint8_t* data, uint16_t size)
        {
            while (size--) transfer(*data++);
        }
 
        void transfer(uint8_t* data, uint16_t size, uint8_t sent)
        {
            while (size--) *data++ = transfer(sent);
        }
 
        void transfer(uint16_t size, uint8_t sent)
        {
            while (size--) transfer(sent);
        }
 
    private:
        using REG8 = board_traits::REG8;
#ifdef SPDR
        static constexpr const REG8 SPDR_{SPDR};
        static constexpr const REG8 SPSR_{SPSR};
#else
        static constexpr const REG8 USIDR_{USIDR};
        static constexpr const REG8 USISR_{USISR};
        static constexpr const REG8 USICR_{USICR};
#endif
    };
 
    template<board::DigitalPin CS, ChipSelect CS_MODE = ChipSelect::ACTIVE_LOW, ClockRate RATE = ClockRate::CLOCK_DIV_4,
             Mode MODE = Mode::MODE_0, DataOrder ORDER = DataOrder::MSB_FIRST>
    class SPIDevice : public AbstractSPIDevice
    {
    protected:
        SPIDevice() INLINE = default;
 
#ifdef SPDR
        void start_transfer()
        {
            cs_.toggle();
            SPCR_ = SPCR_START_;
            SPSR_ = SPSR_START_;
        }
#else
        void start_transfer()
        {
            cs_.toggle();
            // Set 3-wire mode (SPI) and requested SPI mode (0 or 1) and use software clock strobe (through USITC)
            USICR_ = USICR_START_;
        }
#endif
        void end_transfer() INLINE
        {
            cs_.toggle();
        }
 
    private:
        using REG8 = board_traits::REG8;
#ifdef SPDR
        static constexpr const REG8 SPCR_{SPCR};
        static constexpr const REG8 SPDR_{SPDR};
        static constexpr const REG8 SPSR_{SPSR};
        // Configuration values to reset at beginning of each transfer
        static const constexpr uint8_t SPCR_START_ =
            bits::BV8(SPE, MSTR) | (uint8_t(RATE) & 0x03U) | uint8_t(ORDER) | uint8_t(MODE);
        static const constexpr uint8_t SPSR_START_ = (uint8_t(RATE) & 0x10U) ? bits::BV8(SPI2X) : 0;
#else
        static constexpr const REG8 USIDR_{USIDR};
        static constexpr const REG8 USISR_{USISR};
        static constexpr const REG8 USICR_{USICR};
        static const constexpr uint8_t USICR_START_ = uint8_t(MODE);
#endif
        gpio::FAST_PIN<CS> cs_ = gpio::FAST_PIN<CS>{gpio::PinMode::OUTPUT, CS_MODE == ChipSelect::ACTIVE_LOW};
    };
};
 
#endif /* FASTSPI_HH */